Notes · ElectronicsUK · A-Levels

Sequential logic systems

Sequential logic adds memory to the gates of the previous chapter: its outputs depend on past inputs as well as present ones. This chapter develops the NAND latch as a one-bit store, the edge-triggered D-type flip-flop, and the ripple, decade and synchronous counters and registers built from them, including their use as frequency dividers.

4 sections~15 min reading time3 competenciesLevel Standard 2 · Advanced 2

T·0555 / 16

Exam profile

AO1 · Describe the NAND latch, the D-type flip-flop and ripple, decade and synchronous counters.AO2 · Complete flip-flop timing diagrams and counter state sequences and calculate division ratios.AO3 · Design a divide-by-n counter and choose the reset logic to give a required modulus.

Operators:describecompletedeterminedesignanalysecalculateevaluate

basic level

At AS the focus is the NAND latch as a memory element and the D-type flip-flop, including its use to divide a clock by two.

higher level

The full A-Level develops multi-stage ripple counters, modulo-n and decade counters with reset logic, synchronous counters and shift registers.

Depth

Text

Contents · 4 sections

Sequential logic systems

The NAND latch#

StandardWJEC/Eduqas A Level Electronics — Unit 2 Digital Electronics (latches)

Cross-coupled NAND latch

Fig. 1The two NAND gates are cross-coupled: each output feeds back to the other gate's input, giving the circuit its memory.

A latch is the simplest memory element: a circuit that can hold a single bit indefinitely. The set-reset (SR) latch is built from two NAND gates cross-coupled, so that each gate's output feeds back to an input of the other. This feedback is what gives the circuit memory — its output depends not only on the present inputs but on the state it is already in, which is the defining feature of sequential logic.

The NAND latch has two active-low inputs, conventionally labelled

\overline{S}

(set) and

\overline{R}

(reset), and two complementary outputs

Q

and

\overline{Q}

. Taking

\overline{S}

low (to 0) forces

Q

to 1 (set); taking

\overline{R}

low forces

Q

to 0 (reset). With both inputs high (their inactive state) the latch simply holds whatever it was last set to — the memory condition. This is how a single bit is stored: pulse one input to write it, then leave both inputs inactive to retain it.

One input combination must be avoided. Taking both

\overline{S}

and

\overline{R}

low at the same time drives both outputs to 1, so

Q

and

\overline{Q}

are no longer complementary — the outputs are ambiguous, and when the inputs are released the final state is unpredictable. This is the forbidden (invalid) state of the SR latch, and any design must ensure the two inputs are never asserted together. Recognising and explaining this forbidden state is a standard exam point.

The classic application of a latch is switch debouncing. A mechanical switch bounces as its contacts make and break, producing a burst of spurious pulses that would confuse a counter. A latch set by the first clean contact ignores the subsequent bounces, delivering a single clean transition. This turns a messy real-world input into a reliable digital signal — a direct example of the input-conditioning stage of a digital system.

The latch is level-sensitive: its output can change at any time an input is active. Most sequential systems instead need a store that changes only at a precisely defined instant, so that many bits can be updated together and in step with a clock. Adding gating and edge-detection to the basic latch produces the flip-flop of the next section, which is the true workhorse of counters and registers. The latch is the conceptual seed from which all of them grow.

Q_{next} = \begin{cases} 1 & \overline{S}=0,\ \overline{R}=1 \\ 0 & \overline{S}=1,\ \overline{R}=0 \\ Q & \overline{S}=1,\ \overline{R}=1 \end{cases}

NAND latch behaviour

Active-low set and reset, with a hold state; both inputs low is forbidden.

NAND latch truth table

Fig. 2The four input conditions of the NAND latch: set, reset, hold, and the forbidden state where both outputs go high.

Worked example

Tracking a latch through an input sequence

A NAND latch starts with $Q=0$ . The inputs $(\overline{S},\overline{R})$ are applied in the order $(0,1)$ , then $(1,1)$ , then $(1,0)$ , then $(1,1)$ . Find $Q$ after each step.

Step 1: (0,1)
$\overline{S}=0$ sets the latch, so $Q=1$ .
Step 2: (1,1)
Both inputs inactive: the latch holds, so $Q$ stays at 1.
Step 3: (1,0)
$\overline{R}=0$ resets the latch, so $Q=0$ .
Step 4: (1,1)
Hold again: $Q$ stays at 0.

Result: $Q$ follows $1, 1, 0, 0$ — the latch stores each command until the next set or reset, demonstrating one bit of memory.

Typical mistakes

Forgetting that the NAND latch inputs are active-low, so a 0 (not a 1) sets or resets it.
Overlooking the forbidden state where both inputs are asserted and the outputs are no longer complementary.

Active revision

For a NAND (SR) latch, state the output $Q$ that results from each input pair $(\overline{S},\overline{R})$ : (1,1), (0,1), (1,0) and (0,0), and identify which is forbidden.

Active recall

Recall the key points — then reveal.

Sources: WJEC/Eduqas GCE Electronics specification (WJEC / Eduqas)

The D-type flip-flop#

StandardWJEC/Eduqas A Level Electronics — Unit 2 Digital Electronics (D-type flip-flop)

D-type flip-flop truth table

Fig. 3The D-type captures

D

on the rising clock edge; with no edge it holds its output regardless of

D

A flip-flop is an edge-triggered store: its output changes only at a precise instant, the rising (or falling) edge of a clock signal, and holds steady at all other times. The D-type (data) flip-flop is the most useful. It has a data input

D

, a clock input, and outputs

Q

and

\overline{Q}

. Its rule is beautifully simple: on the active clock edge,

Q

takes the value of

D

; between edges, whatever

D

does,

Q

does not change.

Edge triggering is the key improvement over the level-sensitive latch. Because the D-type samples

D

only at the clock edge, many flip-flops driven by the same clock all capture their inputs at exactly the same instant, keeping a whole system in step. This synchronous updating is what makes reliable counters, registers and processors possible; without it, signals rippling through a circuit at slightly different times would produce glitches and race conditions.

Connecting the inverted output

\overline{Q}

back to the data input turns a D-type into a toggle (T) flip-flop. Now, on each clock edge,

Q

is loaded with the opposite of its present value, so it flips between 0 and 1 on every edge. The output therefore changes state once per clock cycle, which means it completes one full cycle for every two input cycles — the flip-flop divides the clock frequency by exactly two. This single trick is the basis of every binary counter.

Real D-types usually add asynchronous set and reset (often called preset and clear) inputs that force

Q

to 1 or 0 immediately, overriding the clock. These are used to initialise a counter to a known state or to force a reset when a particular count is reached, as in the decade counter. Understanding that these inputs act at once, regardless of the clock, while

D

acts only on the clock edge, is important when reading and completing timing diagrams.

The D-type flip-flop is the fundamental one-bit register: it captures and holds a single bit on command. Chaining several so that data shifts from one to the next on each clock edge makes a shift register, used for serial-to-parallel conversion and delay; driving each from the previous stage's output makes a counter. Almost every clocked digital system is, at bottom, an arrangement of D-type flip-flops around combinational logic — which is why mastering this one device unlocks the rest of the sequential unit.

Q_{next} = D \ \text{(on the active clock edge)}

D-type rule

The output takes the data value at the clock edge and holds it otherwise.

f_{out} = \dfrac{f_{clk}}{2} \ \text{(toggle connection)}

Divide by two

With Q-bar fed back to D, the output toggles each edge, halving the frequency.

Worked example

The toggle flip-flop as a divider

A D-type flip-flop is wired with $\overline{Q}$ connected to $D$ and clocked at $8\,\text{kHz}$ . Starting from $Q=0$ , list the output after the first four clock edges and state the output frequency.

Edge 1
$D = \overline{Q} = \overline{0} = 1$ , so on the edge $Q \to 1$ .
Edge 2
$D = \overline{Q} = \overline{1} = 0$ , so $Q \to 0$ . Edges 3 and 4 continue $1$ then $0$ .
Frequency
$Q$ completes one full cycle (0,1,0,1) for every two clock cycles, so $f_{out} = f_{clk}/2 = 8/2 = 4\,\text{kHz}$ .
$f_{out} = \dfrac{8\,\text{kHz}}{2} = 4\,\text{kHz}$

Result: $Q$ toggles $1,0,1,0$ on successive edges, giving a $4\,\text{kHz}$ square wave — the clock divided by two.

Typical mistakes

Letting Q follow D between clock edges — the D-type only samples D at the active edge.
Confusing the divide-by-two output frequency with the clock frequency (the output is half).

Active revision

A D-type flip-flop has its $\overline{Q}$ output connected to its $D$ input and is clocked at $2\,\text{kHz}$ . Describe the output waveform at $Q$ and state its frequency.

Active recall

Recall the key points — then reveal.

Sources: WJEC/Eduqas GCE Electronics specification (WJEC / Eduqas)

Ripple counters and frequency division#

AdvancedWJEC/Eduqas A Level Electronics — Unit 2 Digital Electronics (counters)

Four-stage ripple counter

Fig. 4Each toggle flip-flop divides by two, so the four outputs

Q_0

Q_3

count in binary and the last stage is the clock divided by 16.

Chaining toggle flip-flops makes a binary counter. The clock drives the first flip-flop, whose output toggles at half the clock frequency; that output clocks the second flip-flop, whose output toggles at a quarter of the clock; and so on. Each stage divides the frequency by a further two, and the flip-flop outputs, read together, count upward in binary. Because each stage is clocked by the previous stage's output, the changes 'ripple' along the chain — hence the name ripple counter.

With

n

flip-flops the counter has

2^n

distinct states, counting from 0 up to

2^n - 1

before rolling over to zero. Four flip-flops therefore give a modulo-16 counter that counts

0000

1111

(0 to 15) and divides the input frequency by 16 at the final output. This is the standard way to build a frequency divider: to divide a clock by

2^n

, use

n

toggle flip-flops and take the output of the last stage.

The counter's outputs form a natural binary number, with the first stage as the least significant bit. Reading the state sequence shows the least significant bit changing on every clock, the next bit changing half as often, and so on — exactly the binary counting pattern. This makes the ripple counter simultaneously a counter (its outputs are the count) and a set of frequency dividers (each output is the clock divided by a power of two), and questions exploit both interpretations.

Ripple counters are simple and cheap but have a weakness: because each stage must wait for the previous one to change, the effect of a clock edge takes time to propagate along the chain. During this brief settling time the outputs pass through incorrect intermediate values, so a ripple counter can produce short-lived wrong states and is not suitable where the outputs are decoded at high speed. This propagation delay is the trade-off for the ripple counter's simplicity and is the reason synchronous counters exist.

As a system block, a counter is a memory-bearing process stage that turns a stream of clock pulses into a running total. It is used to divide frequencies (as in the timing of the seconds in a clock, derived by dividing a crystal oscillator), to count events from a sensor, and to generate the address sequence that steps a system through a set of operations. Recognising that counting and frequency division are two views of the same circuit is the key insight of this section.

\text{states} = 2^n, \quad \text{max count} = 2^n - 1

Counter capacity

n flip-flops give 2^n states counting 0 to 2^n minus 1.

f_{stage\,k} = \dfrac{f_{clk}}{2^k}

Frequency division

The k-th stage output is the clock divided by two to the power k.

Ripple counter timing

Fig. 5Timing of the first three outputs:

Q_0

toggles every clock,

Q_1

half as often and

Q_2

half again — each stage divides by two.

Worked example

Designing a frequency divider

A ripple counter must divide a $32\,\text{kHz}$ clock to $2\,\text{kHz}$ . Find the number of flip-flops needed, the counter's modulus and the frequency at each stage.

Division ratio
$32\,\text{kHz} \div 2\,\text{kHz} = 16$ , so the clock must be divided by $16 = 2^4$ .
Number of flip-flops
Dividing by $2^4$ needs $4$ toggle flip-flops; the counter is modulo-16 (states 0 to 15).
Stage frequencies
The stage outputs are $32/2 = 16\,\text{kHz}$ , $16/2 = 8\,\text{kHz}$ , $8/2 = 4\,\text{kHz}$ and $4/2 = 2\,\text{kHz}$ at the last stage.
$f_{out} = \dfrac{32\,\text{kHz}}{2^4} = 2\,\text{kHz}$

Result: Four flip-flops (modulo-16) give stage frequencies $16, 8, 4$ and $2\,\text{kHz}$ , the last being the required output.

Typical mistakes

Confusing the number of states ( $2^n$ ) with the maximum count ( $2^n - 1$ ).
Ignoring propagation delay and assuming a ripple counter's outputs change simultaneously.

Active revision

A ripple counter must divide a $32\,\text{kHz}$ clock down to $1\,\text{kHz}$ . How many flip-flops are needed, what is the counter's modulus, and what is the frequency at each intermediate stage?

Active recall

Recall the key points — then reveal.

Sources: WJEC/Eduqas GCE Electronics specification (WJEC / Eduqas)

Modulo-n and synchronous counters#

AdvancedWJEC/Eduqas A Level Electronics — Unit 2 Digital Electronics (modulo-n, synchronous)

Decade counter state sequence

Fig. 6The decade counter runs 0 to 9; on the pulse that would make ten (

1010

) the reset logic clears it back to 0, giving ten states.

A plain binary counter counts to a power of two, but many applications need a different modulus — a decade counter that counts 0 to 9, or a divide-by-six for seconds and minutes. A modulo-

n

counter is made by letting a full binary counter run and detecting the moment it reaches

n

, then using that detection to reset every flip-flop to zero. The counter therefore cycles through the states 0 to

n-1

and jumps back to 0 on the count that would have been

n

The decade counter is the standard example. A four-bit counter is allowed to count normally until it reaches ten, which in binary is

1010

. A gate that detects this pattern — an AND gate fed from the outputs that are 1 in

1010

, namely

Q_1

and

Q_3

— produces a pulse the instant the count reaches ten, and that pulse is fed to the reset inputs. The result is a counter that runs

0000

through

1001

(0 to 9) and then resets, giving ten states — a decade.

Choosing the reset logic is the design skill. To make a modulo-

n

counter you write

n

in binary, identify which outputs are 1 in that pattern, and AND those outputs together to drive the reset. For a divide-by-six counter,

n=6=110

, so you AND

Q_1

and

Q_2

; for divide-by-ten you AND

Q_1

and

Q_3

. The counter never actually settles at the detected state — it appears only momentarily before the reset clears it — so the useful sequence is 0 to

n-1

Ripple counters, even when given reset logic, still suffer propagation delay, so for higher speeds a synchronous counter is used. In a synchronous counter every flip-flop is clocked by the same clock at the same instant, and combinational logic between the flip-flops decides which ones should toggle on each edge. Because all the outputs change together, there are no rippling intermediate states, so the outputs are clean and can be decoded reliably at high clock rates.

The trade-off is clear and examinable: a ripple counter is simpler and needs less logic but is slower and can glitch; a synchronous counter needs extra gating between the stages but is fast and glitch-free. Real counter chips are usually synchronous for this reason. Being able to design a modulo-

n

counter's reset logic, and to justify the choice between ripple and synchronous operation for a given speed requirement, is exactly the analyse-and-design reasoning the A2 paper rewards.

\text{reset when count} = n \ (\text{AND of the outputs that are 1 in } n_2)

Modulo-n reset

Detect the binary pattern of n and use it to clear the counter.

Worked example

Reset logic for a modulo-6 counter

Design the reset logic for a divide-by-six (modulo-6) counter made from a binary counter, and list the states it cycles through.

Binary of the modulus
$n = 6 = 110$ in binary, so the outputs that are 1 are $Q_2$ and $Q_1$ .
Reset gate
An AND gate fed from $Q_2$ and $Q_1$ goes high exactly when the count reaches $110$ ; its output drives the flip-flop resets.
State sequence
The counter runs $000, 001, 010, 011, 100, 101$ (0 to 5); on the next pulse it momentarily reaches $110$ , the AND fires, and it resets to $000$ .

Result: AND $Q_1$ and $Q_2$ to drive the reset; the counter cycles through the six states 0 to 5 before returning to 0.

Typical mistakes

Detecting the wrong count for reset — a decade counter resets on ten ( $1010$ ), giving states 0 to 9.
Claiming a modulo-n counter has n+1 useful states; the detected state is cleared at once, leaving n states (0 to n-1).

Active revision

Design the reset logic for a modulo-6 counter built from a binary counter, and state the sequence of states it produces.

Active recall

Recall the key points — then reveal.

Sources: WJEC/Eduqas GCE Electronics specification (WJEC / Eduqas)

References & sources

Sources

WJEC / Eduqas

WJEC/Eduqas GCE Electronics specification

Sequential logic systems

4 sections~15 min reading time3 competenciesLevel Standard 2 · Advanced 2

Sequential logic systems

Key points

Tracking a latch through an input sequence

Key points

The toggle flip-flop as a divider

Key points

Designing a frequency divider

Key points

Reset logic for a modulo-6 counter

Sources

Sequential logic systems

Key points

Tracking a latch through an input sequence

Key points

The toggle flip-flop as a divider

Key points

Designing a frequency divider

Key points

Reset logic for a modulo-6 counter

Sources