Notes · Computer ScienceUK · A-Levels

Fundamentals of computer organisation and architecture

This chapter opens up the processor. It sets out the internal components and the stored-program concept, the von Neumann and Harvard architectures, the registers, arithmetic-logic unit, control unit and buses that make up the CPU, and the fetch-execute cycle that drives everything. It then descends to machine code and assembly with its addressing modes, and finishes with the factors that determine performance and the storage and embedded systems that surround the processor.

5 sections~17 min reading time3 competenciesLevel Foundation 1 · Standard 2 · Advanced 2

T·0777 / 14

Exam profile

AO1 · Know the internal components, the stored-program concept, the register set, the buses and the addressing modesAO2 · Describe the fetch-execute cycle in register-transfer terms and trace simple assembly/machine-code programsAO3 · Evaluate the factors affecting processor performance and architectural choices

Operators:describeexplaintracecomparecalculateevaluate

basic level

AS-Level expects the CPU components, the stored-program concept and the outline of the fetch-execute cycle.

higher level

The full A-Level adds the detailed register-transfer fetch-execute cycle, interrupts, addressing modes, assembly-language tracing, and reasoned evaluation of performance factors.

Depth

Text

Contents · 5 sections

Fundamentals of computer organisation and architecture

Internal components and the stored-program concept#

FoundationAQA 7517 4.7.1DfE GCE Computer Science - architecture

The von Neumann architecture

Fig. 1The CPU, main memory and I/O controllers all connect to a single shared system bus carrying address, data and control signals. Instructions and data share the one memory and the one bus - flexible, but only one can be fetched at a time (the von Neumann bottleneck).

A computer has three essential kinds of internal component connected by a communication path. The processor (CPU) fetches and executes instructions; main memory (RAM) holds the instructions and data currently in use; and input/output controllers connect to peripherals and storage. They are joined by the system bus (shown opposite), a set of parallel wires carrying addresses, data and control signals between them. This three-part organisation - processor, memory, buses to input/output - is the skeleton of every general-purpose computer.

The stored-program concept, the foundational idea due to von Neumann, is that a program's instructions are stored in the same memory as its data, in the same binary form, and are fetched and executed one after another. This is what makes a computer general-purpose: to run a different task you simply load a different program into memory rather than rewire the machine. Because instructions are just data in memory, a program can even be written or modified by another program - the principle behind compilers, operating systems and the universal Turing machine.

The von Neumann architecture realises this with a single memory and a single bus shared by both instructions and data. Its simplicity and flexibility made it the dominant design, but the shared path is also its weakness: instructions and data cannot be fetched at the same time, a limitation called the von Neumann bottleneck. The Harvard architecture instead uses separate memories and buses for instructions and data, so both can be accessed simultaneously - faster, and common in embedded systems and digital signal processors where instructions are fixed in ROM.

In practice modern processors are a hybrid: a von Neumann main memory with Harvard-style separate instruction and data caches close to the core, gaining much of Harvard's parallelism while keeping von Neumann's flexible single main memory. Being able to describe the stored-program concept and contrast the two architectures - including why Harvard can be faster and why von Neumann is more flexible - is standard AO1/AO3 content.

Worked example

Why instructions and data sharing memory matters

Explain, using the stored-program concept, how the same physical computer can run a word processor one moment and a game the next without any hardware change.

Programs are data in memory
Under the stored-program concept a program is just a sequence of binary instructions held in main memory, indistinguishable in form from data.
Loading swaps the program
To switch task the operating system loads a different program's instructions into memory; the CPU then fetches and executes those instead.
The hardware is unchanged
The fetch-execute cycle is identical whatever the instructions are, so no rewiring is needed - only the memory contents differ.

Result: Because instructions live in changeable memory, one general-purpose machine runs any program simply by loading it - the essence of the stored-program computer.

Typical mistakes

Thinking von Neumann uses separate memories for programs and data - that is Harvard; von Neumann shares one memory and bus.
Confusing main memory (RAM, volatile, holds current programs and data) with secondary storage (persistent, holds files long-term).

Active revision

Explain the stored-program concept and state one advantage and one disadvantage of the von Neumann architecture compared with the Harvard architecture.

Active recall

Recall the key points — then reveal.

Sources: GCE AS and A level subject content for computer science (Department for Education) · AQA A-level Computer Science 7517 specification (AQA)

The CPU: registers, ALU, control unit and buses#

StandardAQA 7517 4.7.2DfE GCE Computer Science - CPU structure

The CPU registers and their roles

Fig. 2The special-purpose registers used by the fetch-execute cycle. The PC and CIR track which instruction is running; the MAR and MBR move addresses and data to and from memory; the accumulator and status register hold ALU results and condition flags.

The CPU contains three main parts working together. The arithmetic-logic unit (ALU) performs all calculations (addition, subtraction, shifts) and logical operations (AND, OR, comparisons). The control unit (CU) directs everything: it decodes each instruction and generates the timing and control signals that move data between components and tell the ALU what to do. And a set of very fast registers - small on-chip stores - hold the values the CPU is working on right now.

The registers each have a defined job and are listed opposite. The program counter (PC) holds the address of the next instruction to fetch. The memory address register (MAR) holds the address currently being accessed, and the memory buffer/data register (MBR/MDR) holds the data or instruction just read from, or about to be written to, memory. The current instruction register (CIR) holds the instruction being decoded and executed. The accumulator (ACC) holds the result of ALU operations, and the status register holds condition flags (carry, zero, negative, overflow) set by the ALU. Knowing each register's exact purpose is essential for the fetch-execute cycle.

The CPU communicates with memory over the system bus, which has three parts. The address bus carries the address of the location to access - it is one-directional (CPU to memory), and its width sets how much memory can be addressed:

n

address lines can address

2^{n}

locations. The data bus carries the actual data or instruction and is bidirectional; its width sets how many bits move at once. The control bus carries timing and control signals (read, write, clock, interrupt) that coordinate the transfer.

The width of the buses is a direct performance factor. A wider data bus moves more bits per transfer, and a wider address bus allows more memory to be fitted (a 32-line address bus reaches

2^{32}

= 4 GB of locations, a 64-line bus vastly more). This is exactly why 'word size' and bus width appear in processor specifications, and why the addressable-memory calculation (

2^{n}

locations from

n

address lines) is a standard exam question.

\text{addressable locations} = 2^{n}

Addressable memory

An address bus of $n$ lines can select $2^n$ distinct memory locations; each extra line doubles the range.

Worked example

Addressable memory from bus width

A processor has a 16-line address bus, and each addressable location stores one byte. How much memory can it address? What happens if the address bus is widened to 20 lines?

16 lines
$2^{16} = 65\,536$ locations. At one byte each that is 65 536 bytes = 64 KiB.
20 lines
$2^{20} = 1\,048\,576$ locations = 1 MiB - each extra line doubles the range, so four more lines multiply it by $2^4 = 16$ .

Result: 16 lines address 64 KiB; 20 lines address 1 MiB. Bus width directly limits how much memory a processor can use.

Typical mistakes

Confusing the roles of the MAR (holds the address) and the MBR/MDR (holds the data/instruction), or the PC (next instruction) and the CIR (current instruction).
Thinking the address bus is bidirectional - it is one-way from CPU to memory; only the data bus is bidirectional.

Active revision

State the role of the PC, MAR, MBR and CIR. Then calculate how many memory locations can be addressed with a 16-line address bus, and how the addressable memory changes if two more address lines are added.

Active recall

Recall the key points — then reveal.

Sources: AQA A-level Computer Science 7517 specification (AQA)

The fetch-execute cycle and interrupts#

AdvancedAQA 7517 4.7.3DfE GCE Computer Science - fetch-execute

The fetch-execute cycle

Fig. 3The CPU endlessly repeats fetch (bring the next instruction from memory into the CIR, incrementing the PC), decode (the control unit interprets the opcode and operand) and execute (carry out the operation, storing any result). After executing, an interrupt check may divert to a service routine before the next fetch.

The fetch-execute cycle (also called the fetch-decode-execute cycle) is the fundamental loop the CPU repeats for every instruction, for as long as the computer is on (shown opposite). It is described precisely in register-transfer terms - the movement of values between the registers - and this precise description is exactly what the exam rewards, so it is worth learning as a sequence of register transfers rather than vague prose.

The fetch phase brings the next instruction from memory into the CPU: the address in the PC is copied to the MAR (

\text{PC} \rightarrow \text{MAR}

); the control unit signals a memory read, so the instruction at that address travels down the data bus into the MBR (

\text{MEM[MAR]} \rightarrow \text{MBR}

); the PC is incremented to point at the following instruction (

\text{PC} + 1 \rightarrow \text{PC}

); and the fetched instruction is copied from the MBR into the CIR (

\text{MBR} \rightarrow \text{CIR}

), ready to be interpreted.

In the decode phase the control unit examines the instruction now in the CIR, splitting it into its opcode (which operation) and its operand (which data or address), and works out what control signals are needed. In the execute phase those signals are issued: the operation is carried out - the ALU adds or compares, a value is loaded from or stored to memory, or the PC is changed for a jump - and any result is placed in the accumulator. The cycle then returns to fetch the next instruction, whose address the incremented PC already holds.

An interrupt is a signal from hardware or software that an event needs immediate attention (a key press, a completed disk transfer, an error). At the end of the current cycle the CPU checks for interrupts; if one is present and of high enough priority, it saves its current state (the register contents, especially the PC) onto the stack, runs the appropriate interrupt service routine (ISR), then restores the saved state and resumes exactly where it left off. Interrupts let a processor respond promptly to events without constantly polling for them, and are the mechanism behind multitasking and responsive I/O.

Worked example

The fetch phase as register transfers

Write out, in order, the register transfers that make up the fetch phase of the fetch-execute cycle, explaining each.

PC to MAR
The address of the next instruction, held in the program counter, is copied into the memory address register so memory can be told which location to read. ( $\text{PC} \rightarrow \text{MAR}$ )
Memory to MBR
The control unit asserts a read on the control bus; the instruction at address MAR travels along the data bus into the memory buffer register. ( $\text{MEM[MAR]} \rightarrow \text{MBR}$ )
Increment PC
The program counter is incremented so it now points to the following instruction. ( $\text{PC} + 1 \rightarrow \text{PC}$ )
MBR to CIR
The fetched instruction is transferred from the buffer to the current instruction register, ready for the control unit to decode. ( $\text{MBR} \rightarrow \text{CIR}$ )

Result: After the fetch, the instruction is in the CIR and the PC already points to the next one, so decoding and execution can proceed and the cycle can repeat cleanly.

Typical mistakes

Getting the register transfers in the wrong order, or forgetting to increment the PC during the fetch phase.
Saying the PC holds the current instruction - it holds the address of the next one; the CIR holds the current instruction.

Active revision

Write out the fetch phase of the fetch-execute cycle as a sequence of register transfers, then explain what the CPU does with its registers when a higher-priority interrupt arrives during execution.

Active recall

Recall the key points — then reveal.

Sources: AQA A-level Computer Science 7517 specification (AQA)

Machine code, addressing modes and assembly#

AdvancedAQA 7517 4.7.4DfE GCE Computer Science - machine code

The four addressing modes

Fig. 4How the operand of an instruction is interpreted. Immediate uses the operand as the value; direct uses it as the address of the value; indirect uses it as the address of a location holding the address of the value (a pointer); indexed adds an index register to form the effective address (ideal for arrays).

A machine-code instruction is a binary pattern in two parts: an opcode, which says what to do (load, store, add, jump), and one or more operands, which say what to do it to (a value, a memory address, or a register). Assembly language gives each opcode a readable mnemonic (LDA to load, STA to store, ADD, SUB, BRA to branch) in a one-to-one correspondence with machine instructions, so a single assembly instruction assembles to a single machine instruction. This is the lowest level a human normally programs at, met through simplified models such as the Little Man Computer (LMC).

Addressing modes answer a subtle but vital question: how should the operand be interpreted? The four required modes are listed opposite. In immediate addressing the operand is the value to use (

\texttt{LDA \#40}

loads the number 40). In direct addressing the operand is the address holding the value (

\texttt{LDA 40}

loads the contents of location 40). In indirect addressing the operand is the address of a location that itself holds the address of the value - a pointer - allowing flexible, run-time-determined access. In indexed addressing the effective address is the operand plus the contents of an index register, which makes stepping through an array simple by incrementing the index.

The addressing modes exist because different tasks need the operand read differently: immediate for constants, direct for named variables, indirect for pointers and dynamic structures, and indexed for arrays and loops. Being able to state what each mode does and to work out the effective address and the value loaded is a standard, high-value exam skill, and mixing up direct with immediate (loading an address as if it were a value, or vice versa) is a classic error.

A short assembly/LMC program is traced by stepping through the instructions and keeping the accumulator and any referenced memory locations up to date, exactly as the fetch-execute cycle would. A program that inputs two numbers, stores one, adds the other and outputs the sum demonstrates the load-store nature of the machine: arithmetic happens in the accumulator, and values are shuttled between the accumulator and named memory locations. Tracing such a program, and predicting its output, is routinely examined.

Worked example

Tracing a Little Man Computer program

Trace the LMC program: INP; STA 99; INP; ADD 99; OUT; HLT with inputs 3 then 5. Give the accumulator and location 99 after each instruction, and the output.

INP; STA 99
First input: ACC = 3. STA 99 stores the accumulator into mailbox 99, so location 99 = 3 (ACC still 3).
INP
Second input overwrites the accumulator: ACC = 5. Location 99 is unchanged at 3.
ADD 99
Add the contents of location 99 to the accumulator: ACC = $5 + 3 = 8$ .
OUT; HLT
OUT outputs the accumulator, 8; HLT stops the program.

Result: The program outputs 8. It shows the load-store pattern: values move between the accumulator and memory, and the ALU adds through the accumulator.

Typical mistakes

Confusing immediate (operand is the value) with direct (operand is the address of the value) addressing.
Forgetting that arithmetic in a simple accumulator machine goes through the accumulator - you must load, operate, then store.

Active revision

For a location 50 that contains the value 8, and an index register X = 3, state the value loaded by each of LDA #50, LDA 50, and LDA 50,X (assume location 53 contains 20). Then trace an LMC program that inputs two numbers and outputs their sum.

Active recall

Recall the key points — then reveal.

Sources: AQA A-level Computer Science 7517 specification (AQA)

Performance, I/O, storage and embedded systems#

StandardAQA 7517 4.7.5AQA 7517 4.7.6DfE GCE Computer Science - performance and storage

Several factors together determine a processor's performance. Clock speed (in gigahertz) sets how many fetch-execute cycles occur per second - a higher clock does more work per second, but only up to the limits of heat and power. The number of cores lets a processor genuinely execute several instruction streams in parallel, though the speed-up is limited by how well a task can be split and by shared resources - doubling the cores rarely doubles real performance. Cache is a small amount of very fast memory on or near the CPU that holds recently used instructions and data, cutting the time wasted waiting for slow main memory; more cache, and more levels of it, raises the hit rate and so the speed.

Word length (the number of bits the CPU handles at once) and bus widths also matter, as met earlier: wider data paths move more per cycle and wider address buses reach more memory. Real performance is a balance of all these - a fast clock is wasted if the processor constantly stalls waiting for memory, which is why cache and bus design matter as much as raw clock speed. Evaluating which factor most helps a given workload is a typical AO3 question.

Secondary storage keeps programs and data permanently (non-volatilely), unlike volatile RAM. There are three main technologies. Magnetic storage (hard disk drives) stores bits as magnetised regions on spinning platters - high capacity and low cost per byte, but slower and mechanically fragile. Solid-state/flash storage (SSDs, USB drives, memory cards) stores bits in flash memory cells with no moving parts - fast, silent and shock-resistant, but dearer per byte and with a finite number of write cycles. Optical storage (CD, DVD, Blu-ray) stores bits as pits read by a laser - cheap and removable but low capacity and slow. Choosing the right medium is a trade-off of capacity, speed, cost, durability and portability.

An embedded system is a computer built into a larger device to perform a dedicated function - the controller in a washing machine, a car's engine management, a pacemaker, a router. Embedded systems typically have a fixed program (often in ROM), limited memory and power, real-time requirements, and no general-purpose interface, and they frequently use the Harvard architecture for its speed. They vastly outnumber general-purpose computers, and recognising the constraints that shape them (low power, real-time response, dedicated task) is examined.

Typical mistakes

Assuming doubling the clock speed or the number of cores doubles real performance - gains are limited by heat, memory stalls and how parallelisable the task is.
Confusing main memory (RAM, volatile working memory) with secondary storage (non-volatile, long-term), or calling an SSD 'magnetic'.

Active revision

A laptop is slow when switching between many open programs. Explain how increasing the amount of RAM, the cache size and the number of cores might each help, and recommend the most relevant change. Then compare an HDD and an SSD for a laptop.

Active recall

Recall the key points — then reveal.

Sources: GCE AS and A level subject content for computer science (Department for Education)

References & sources

Sources

Department for Education

GCE AS and A level subject content for computer science

AQA

AQA A-level Computer Science 7517 specification

Fundamentals of computer organisation and architecture

5 sections~17 min reading time3 competenciesLevel Foundation 1 · Standard 2 · Advanced 2

Fundamentals of computer organisation and architecture

Key points

Why instructions and data sharing memory matters

Key points

Addressable memory from bus width

Key points

The fetch phase as register transfers

Key points

Tracing a Little Man Computer program

Key points

Sources

Fundamentals of computer organisation and architecture

Key points

Why instructions and data sharing memory matters

Key points

Addressable memory from bus width

Key points

The fetch phase as register transfers

Key points

Tracing a Little Man Computer program

Key points

Sources